1. Field of the Invention
The present invention relates to a liquid crystal display, and more particular to a gate driver on array (GOA) circuit and a liquid crystal display device.
2. Description of Related Art
In an active matrix liquid crystal display device, each pixel has a thin film transistor (TFT), the gate of the TFT is connected to a horizontal scanning line, the drain of the TFT is connected to a vertical data line, and the source of the TFT is connected to a pixel electrode. Applying sufficient voltage on the horizontal scanning line, every TFT on the horizontal scanning line will be turned on. The horizontal scanning lines are connected to the vertical data line in order to write a display signal voltage on the data line to the pixel, and achieve the effect of controlling the color through controlling different transmittance of the liquid crystals.
Currently, the driving of the horizontal scanning lines of an active matrix liquid crystal display (LCD) panel is using an external IC connected at the outside of the panel. The external IC can control every stage of the horizontal scanning lines to charge and discharge.
The gate driver on array (GOA) technology can utilize the original fabrication process of the LCD panel to fabricate a driving circuit of the horizontal scan lines on the substrate around the display region such that the driving circuit can replace the external IC to drive the horizontal scan lines. The GOA technology can reduce the bonding process for the external IC to increase productivity and reduce product cost such that the LCD panel is more suitable for the narrow frame or no frame display product.
The conventional GOA circuit generally includes multiple cascaded GOA units; each of the GOA units corresponds to drive a stage of horizontal scanning line. The GOA unit mainly includes a pull-up circuit, a pull-up control circuit, a transfer circuit, a pull-down circuit, a pull-down holding circuit, and a boast capacitor used to boost a voltage. Wherein the pull-up circuit is mainly responsible for outputting a clock signal as a gate signal; the pull-up control circuit is responsible for controlling a turn-on time of the pull-up circuit, and generally connected to a transfer signal or a gate signal from the previous stage GOA unit; the pull-down circuit is responsible for pulling down the gate signal to a low level voltage immediately, that is, turning off the gate signal; the pull-down holding circuit is responsible for holding a gate output signal or the gate signal of the pull-up circuit (commonly referred to as a Q node) at a turn-off state (i.e., a negative voltage). Usually, two pull-down holding circuits function alternatively; the boast capacitor is responsible for secondarily boosting the voltage of the Q node to facilitate the G (N) output of the pull-up circuit.
As shown in FIG. 1, a schematic diagram of a conventional GOA circuit is shown. In FIG. 1, a GOA unit comprises: a pull-up control circuit 100, a pull-up circuit 200, a transfer circuit 300, a pull-down circuit 400, a boast capacitor 500, a first pull-down holding circuit 600, a second pull-down holding circuit 700, and a bridge circuit 800. Wherein, the first pull-down holding circuit 600, the second pull-down holding circuit 700, and the bridge circuit 800 form a voltage dividing with three stage resistors.
Wherein, the bridge circuit 800 adjusts voltages at two terminals P (N) and K (N) through the thin film transistor (TFT) T55. The gate of the T55 connects to Q (N). The drain and the source of the T55 respectively connect to P (N) and K (N). In an operation period, the gate of T55 is turned on such that the voltages of P (N) and K (N) are closed in a turn-off state. Because the low level voltage of each of low frequency signals LC1 and LC2 is smaller than VSS such that the voltages of P (N) and K (N) in the operation period is smaller than VSS in order to guarantee and pull down that the Vgs<0 for the TFTs T32 and T33 connected to G (N) and the Vgs<0 for the TFTs T42 and T43 connected to Q (N). Accordingly, current leakage at G (N) and Q (N) in the operation period is prevented.
The first pull-down holding circuit 600 and the second pull-down holding circuit 700 are symmetrical. One function is: in the operation period, the first pull-down holding circuit 600 (or the second pull-down holding circuit 700) is under a turn-off state with a large resistance. At this time, the second pull-down holding circuit 700 (or the first pull-down holding circuit 600) is under a turn-on state with a small resistance, and the bridge circuit 800 is under a turn-on state with a small resistance such that P (N) and K (N) are under low voltage level to guarantee that the voltage boost of the Q (N) node and the output of the G (N) node; Another function is: In a non-operation period, the first pull-down holding circuit 600 and the second pull-down holding circuit 700 are both under a turn-on state with small resistance, and the bridge circuit is under a turn-off state with large resistance. Therefore, high and low voltage levels and alternative function can be achieved at P (N) and K (N).
The gate of the T54 connects to LC2. The drain of the T54 connects to LC1. The source of the T54 connects to P (N). The gate of the T64 connects to LC1. The drain of the T64 connects to LC2. The source of T64 of the T64 connects to L (N). The two TFTs T54 and T64 are called balance TFTs and are used to adjust voltage dividing and rapid discharge when the signal is switching. The gate of the T52 connects to Q (N). The drain of the T52 connects to S (N). The source of the T52 connects to VSS. The gate of T62 connects to Q (N). The drain of the T62 connects to T (N). The source of the T62 connects to VSS. The two TFTs T52 and T62 mainly guarantee pull down the voltages of S (N) and T (N) in the operation period.
Through the GOA unit having voltage dividing with three stages by the first pull-down holding circuit 600, the second pull-down holding circuit 700 and the bridge circuit 800, temperature stability and long-term reliability of the operation of the pull-down holding circuit can be increased, fully utilizing the low frequency signal to realize the switching of P (N) and K (N), and pulling down the voltages of Q (N) and K (N) to lower voltages to decrease the current leakage of Q (N) and G (N) as possible in the operation period. At the same time, in the non-operation period, one of the P (N) and K (N) in a low voltage level is near the low voltage level of LC. Because the low voltage level of LC is smaller than VSS, T32/T42 or T33/T43 is under a negative voltage recovery status in a half time of the operation period. Through adjusting the low voltage level of the low frequency signal, the risk of failure to the pull-down holding circuit can be decreased.
FIG. 2 is a schematic waveform diagram of key nodes of the GOA circuit illustrated in FIG. 1 during actual operation. As shown in FIG. 2, the voltage of the Q (N) node has two time stages. The voltage of the first time stage (t1˜t2) is QV1, and the voltage of the second time stage (t2˜t3) is QV2. The G (N) node will output when Q (N) node is under the second time stage. The P (N) and K (N) are controlled by Q (N) through three TFTs T52, T62, and T55. When Q (N) is at a low voltage level, the P (N) and K (N) are at high voltage levels. On the contrary, when the Q (N) is at a high voltage level, the P (N) and K (N) are at low voltage levels. Therefore, as shown in FIG. 2, because the voltage level at the first time stage QV1 of Q (N) is lower, the voltage level of P (N) and K (N) at the first time stage is higher, that is, PV1>PV2. In this case, the T43, T42, T33, and T32 cannot be turned off well. In other words, Q (N) and G (N) have a larger current leakage, which will also pull down the voltage level in the first time stage QV1 of the Q (N). The voltage in second time stage QV2 of the Q (N) will become lower correspondingly. The pull down holding circuit has a higher risk of failure, and the output of the G (N) will generate a serious delay.
Similarly, because the S (N) node and the T (N) node are also controlled by the Q (N) node. Therefore, the same problem is also existed as P (N) and K (N). In order to compensate the voltage lack in the first time stage voltage of Q (N), the three TFTs T52, T62, T55 are designed to become larger in size. The above way will generate a problem of higher ripple current in the non-operation period of Q (N). As a result, the variation at the high voltage level of S (N) and T (N), and P (N) and K (N) is larger in the non-operation period.